The present invention relates to a semiconductor device (MOS integrated circuit) of a polysilicon gate structure having three or more different Fermi levels and, in particular, to a semiconductor device (MOS integrated circuit) with a DRAM having a polymetal gate.
FIG. 1 shows a semiconductor device (MOS integrated circuit) according to a first related technique. According to the first related technique, all of an NMOS as a memory cell (MC), a peripheral NMOS, and a peripheral PMOS have N+ gates. Therefore, no mask is required to separately form different types of gates. However, the peripheral PMOS having the N+ gate PMOS has a buried channel. This results in inferior short-channel characteristic and low drive power.
FIG. 2 shows a semiconductor device (MOS integrated circuit) according to a second related technique. According to the second related technique, the peripheral PMOS has a P+ gate. With this structure, it is possible to obtain large drive power by improving the short-channel characteristic of the PMOS as a largest problem of the first related technique. In addition, it is possible to reduce a junction field of the memory cell. However, the second related technique is disadvantageous in the following respects.
The concentration of a P type impurity in the P+ gate must be determined primarily so as to reduce the depletion of the peripheral PMOS. This means that the concentration of the P type impurity of the P+ gate must be selected to a relatively high value. As a result, a margin for boron leakage is reduced in both of the memory cell and the peripheral PMOS. Furthermore, in order to obtain high power, two masks are required to form two kinds of gates.
Hereinafter, the disadvantages of the related technique will be described in detail.
First Disadvantage of the Related Technique
It is impossible to simultaneously suppress gate depletion and threshold (Vth) fluctuation due to boron penetration.
FIG. 3 shows heat-treatment dependency of the activation rate of boron injected into the p+ gate. In furnace annealing and furnace CVD in which thermal load is applied for a long time, deactivation of boron in gate polysilicon is remarkable at a temperature not lower than 600 degrees C. Such deactivation results in gate depletion.
FIG. 4 shows the relationship between the electrical oxide thickness in inversion and the gate impurity concentration. As the gate impurity concentration is higher, the gate depletion is more suppressed.
FIG. 5 shows the relationship between the threshold (Vth) fluctuation and the gate impurity concentration. In an n+ gate containing phosphorus injected therein, the Vth fluctuation is smaller as the phosphorus concentration is higher. This is because the degree of carrier degeneration is enhanced as the concentration of phosphorus in the gate is higher, so that the Fermi level of the gate is stable.
On the other hand, in the p+ gate containing boron injected therein, the Vth fluctuation is increased as the boron concentration is higher. This is because the influence of penetration of boron in the gate into the substrate is greater than the effect of the enhancement of carrier degeneration.
Second Disadvantage of the Related Technique
The gate electrode of a dual polymetal structure has a large contact resistance with respect to W/p+(n) polysilicon.
FIG. 6 shows the relationship between the impurity dosage injected into the polysilicon gate and the contact resistance. As regards the n+ gate, the difference in contact resistance is small between the specification of injection of phosphorus alone and the specification of injection of both phosphorus and boron. On the other hand, as regards the p+ gate, the difference in contact resistance is extremely large between the specification of injection of boron alone and the specification of injection of both boron and phosphorus. The contact resistance in the specification of injection of both phosphorus and boron is as large as at least ten times that in the specification of injection of boron alone.
Third Disadvantage of the Related Technique
An n-well is subjected to a large influence of boron penetration.
FIG. 7 shows the Vth fluctuation dependent upon a combination of a conductive type of a gate and a conductive type of a substrate. In the NMOS, the difference in Vth fluctuation between the p+ gate and the n+ gate is 4 mV. On the other hand, in the PMOS, the difference in Vth fluctuation between the p+ gate and the n+ gate is 10 mV. Thus, the influence of boron penetration upon the transistor characteristic is greater with respect to the n-well than to the p-well.
FIG. 8 shows the Vth fluctuation of the PMOS, dependent upon a combination of impurities in the gate polysilicon. In case of the n+(p) gate, the Vth fluctuation is substantially equivalent to that of the n+ gate and, therefore, the influence of boron penetration is negligible.